On VLSI 2020, IMEC published an interesting paper on single-chip CFET, and I had the opportunity to interview one of the authors, airoura Hiroaki. It is well known in the industry that FinFET (FF) is about to reach its calibration life. Samsung has announced that it will switch to horizontal nanosheets (HNS) at 3 nm. TSMC maintains a 3 nm FF, but is expected to move to a new architecture of 2 nm. < / P > < p > assuming intel was still pursuing its own technology, it was expected that Intel would retain 7Nm FF and then migrate to 5nm HNS. < / P > < p > mol is a hole (via) that connects a transistor (foel) with a multilayer wiring (BEOL). Although CO is used by IMEC, there are other options such as Mo, Ru, etc. < p > < p > in this VLSI symposium, there were many articles about 7Nm, 5nm and 3nm published. However, the author found that the application of nanosheet structure of gate all around (GAA) to these nodes is a common global cognition. < / P > < p > at the same time, from the perspective of the technical blueprint, forksheet transistors equipped with buried power rail (BPR) will be used in 2nm, and complex FET (CFET) with BPR will be used in 1nm. < / P > < p > that is to say, in this VLSI forum, IMEC also made a presentation based on the above technical blueprint. The structural changes of FinFET, nanosheet, forksheet and CFET can be clearly seen from the above figure. < / P > < p > CFET structure in the current work, a “monolithic” CFET has been developed by using separate silicon wafers for nFET and pFET, and then bonding them together. In sequence, CFET will manufacture both types of FET on the same silicon chip. < / P > < p > cost advantage of single-chip CFET: in 1 nm, IMEC adopts CFET with NMOS and PMOS vertically arranged (as shown in Figure 8 below). Although the process flow of CFET is very complicated, it undoubtedly greatly reduces the area of CMOS and SRAM and achieves integration. < / P > < p > I find that the starting wafer cost is about 1% higher than that of a standard wafer for two reasons. One is that I don’t believe that sequential CFET requires SOI, and the other is that SOI is about 1% more expensive than standard wafers. The overall approach will also require two starting wafers, not just one. < / P > < p > I think this kind of cost analysis needs more investigation. In the monolithic method, the nFET and pFET are fabricated on separate wafers, so that the manufacturing process of each device can be optimized for that device. The process flow of each chip is shown in Figure 4. < / P > < p > as we move towards N3, n-to-p separation reduces parasitic effects and improves performance. Similarly, by moving from FF to GAA), a gate can be provided on all four sides instead of three, thus improving electrostatic control. Chinese version of K-car: reading a10e design drawing exposure